High speed chip-to-chip interface protocol with scalable bandwidth, low latency and reliable data transfer over serial links. The latest generation supports up to 1.2Tbps bandwidth with support for NRZ and PAM4 serial links.
Interlaken IP is used by many applications including NPU, traffic management and switch fabrics. Open-Silicon, a SiFive company, was a founding member of the Interlaken Alliance and supports silicon-proven Interlaken IP with over 75+ tier 1 customers on various technology and process nodes. The IP includes a validation platform supporting up to 1.2Tbps (64K channels and 48 SerDes lanes) using a wide range of transceiver speeds and Forward Error Correction (FEC) engines.
Extending on the 8th generation of its Interlaken IP core, SiFive now introduces low latency version of the Chip-to-Chip and Die-to-Die connectivity Interlaken IP used across many applications. Cutting edge technologies such as High Performance Computing (HPC) clusters, AI/ML chip clusters, IoT edge devices, networking, and switching fabrics are demanding high throughput data transfer from one chip to another at very low latency. Interlaken-LL includes a validation platform supporting up to 256Gbps.
Best-in class SoC IPs covering wide range of applications from IoT devices, networking and AI/HPC
HBM2/2E IP Subsystem
The HBM2/2E IP is suitable for applications involving graphics, high-performance computing, high-end networking, and communications that require very high bandwidth, lower latency and more density.
Ethernet IP Subsystem
Comprehensive portfolio of fully configurable multi-channel, multi-rate Ethernet MAC, PCS and FEC IP. Support for OIF FlexE in addition to IEEE802.3 standard for data center applications.
USB IP Subsystem
Full range of USB controllers supporting USB2.0/USB3.0/USB3.1 gen1 and gen2 in device mode of operation. Supports AXI interface and in-built DMA features.
Die-to-Die IP Subsystem
Die-to-Die Controller IP offers unique value proposition in terms of low power, high throughput and low latency links enabling faster time to integration for heterogenous chiplet connections in wired communications, AI and HPC applications.